1. Field of the Invention
The present invention is concerned with new dual damascene methods utilizing a partial curing step, a solvent etching step, and a final curing step. These methods result in very thin, cured layers having low biases, even on highly topographic surfaces.
2. Description of the Prior Art
As integrated circuit devices grow smaller, there is an increasing need for multi-level interconnects of smaller size and improved feature integrity. The damascene integration scheme is one way to allow for increasing chip densities on a substrate as design rules continue to shrink integrated circuit devices. The damascene process eliminates the need to etch the metal layer that provides the interconnections, permits more densely spaced interconnects, and eliminates the need for dielectric gap-fill materials.
There are two general classes of damascene processes: single damascene and dual damascene. The single damascene process fabricates interconnections by forming a conducting plug through a dielectric layer to connect to the underlying conducting layer. Another dielectric layer is then formed, with the actual interconnect wiring metallization being patterned in the second layer. The dual damascene process constructs multi-level interconnects of smaller size than the single damascene process. The via and trench patterns are patterned into a single dielectric layer and then filled in one step with a conducting material such as a metal. Dual damascene processes involve fewer steps, resulting in smaller, more complex integrated circuit devices, thus lowering manufacturing complexity and cost.
Despite the advantages of dual damascene processes, patterning and etch processes are made more difficult because of feature topography and more complex stack layers. Several techniques have been developed to address such problems, including self-aligned dual damascene, trench-first dual damascene, and via-first dual damascene processes. The application of self-aligned dual damascene is limited, because it requires a thick, intermediate layer to act as an anti-reflective layer, nearly perfect trench and via alignment, and very high etch selectivity between the dielectric and etch-stop layers. Trench-first dual damascene processes involve first masking and etching the trench, and then aligning the via pattern with the newly etched trenches. Successful trench-first dual damascene processes require achieving very uniform trenches and maintaining critical dimension control of vias, which in turn requires high etch selectivity between the dielectric and etch-stop layers. The use of etch-stop layers may also increase the dielectric constant of the dielectric material, possibly leading to device failure.
Via-first dual damascene is a somewhat simpler technique, because the vias are formed on top of the full stack of layers. The vias are etched, followed by lithography processes to form the trench patterns. Via-first dual damascene requires a fill composition capable of protecting the bottom of the via during the trench etch step, and of planarizing the surface to allow easier trench patterning. Two techniques are commonly used in via-first dual damascene processes: partial fill and full fill. In partial fill processes, the gap-fill material protects only the bottoms of the via holes, requiring consistent coverage and depth control. In full-fill processes, the vias are completely filled and the layer is planarized. The etching process is performed on the top layer. During photoresist patterning steps, it is necessary to control reflections from underlying materials through use of an anti-reflective coating to prevent distortion of the photoresist pattern. If the gap-fill material lacks suitable light-absorbing properties, trench patterning usually requires incorporating an anti-reflective coating into the stack as a hardmask layer, or coating an anti-reflective layer over the gap-fill material before applying the photoresist. These extra layers complicate the process and increase manufacturing costs.
A typical via-first dual damascene process is illustrated in FIG. 1. A dielectric layer (10) is deposited onto a substrate (12) with a conductive layer (14). A gap-fill material without light-absorbing properties (16) has mostly filled the vias (17). A hardmask layer (18) and a bottom anti-reflective coating (20) are applied for reflection control for the patterned photoresist (22) to permit the trench to be etched into the dielectric layer (10).
Using a gap-fill material with good light-absorption and planarizing properties would simplify the process, but conventional organic bottom anti-reflective coatings do not display these properties. Coating properties of bottom anti-reflective coatings vary based on feature density and size. Differences in feature density result in iso-dense bias, in which the depth of the bottom anti-reflective coating is greater in isolated device features than in dense device features. The use of very thick bottom anti-reflective coatings addresses this problem, but requires a troublesome blanket-etch step to planarize the layer and reduce its thickness to more useful levels before the photoresist layer can be applied and patterned. This requires additional manufacturing steps, and may require wafers to be transferred between the etch and lithography bays during manufacturing. Thick coatings also require a high etch selectivity between the photoresist and the bottom anti-reflective coating, which may not be possible because of the etch chemistry or the photoresist and bottom anti-reflective coating chemistries. FIG. 2 shows a dielectric layer (24) with via openings (26) formed over a substrate (28) with a conductive layer (30) that has been coated with a conventional, gap-fill, bottom anti-reflective coating (32). FIG. 2 illustrates the poor fill in the dense areas, nonuniform fill (34), and voids in the bottom anti-reflective coating (36).
Blanket etch steps can also leave debris remaining in device features after etching steps, which can lead to poor electrical connections and device failure. Removal of such debris may require the use of time-consuming, wet-cleaning techniques, and despite this, debris may still remain. Thick bottom anti-reflective coatings can also result in a fence problem in trenches and vias. The bottom anti-reflective coating and the dielectric material undergo a chemical reaction when in contact with one another, forming a thin residue inside the vias. The residue can cause incomplete trench etch, leading to poor device feature integrity. In view of the difficulties in the via-first dual damascene process, a method of using bottom anti-reflective coatings that would reduce the number of steps required in fabrication, eliminate the debris and the fence problems, and result in a more consistent fill of dense and isolated device features is greatly needed.